Interconnections & Assembly

Interconnections & Assembly Research Vision and Strategy

Chip-level Interconnections Assembly and Reliability (CLIAR)

The vision of the chip-level I&A program is to develop and demonstrate a new class of Cu-based interconnection and assembly technologies beyond traditional solder-based approaches, with simultaneous improvements in electrical, thermal and reliability performances and manufacturability and scalability to pitches of 20µm and below, for applications that require these pitches such as high-performance systems. This will be accomplished by bringing innovations in interconnection materials, tools and processes, to extend the applicability of solders by forming all-intermetallics structures as well as to ultimately enable manufacturable all-Cu interconnections without solders. GT PRC’s roadmap for off-chip interconnections is shown below.

Off-chip interconnections roadmap and GT PRC’s R&D focus.

The strategy of the I&A program towards all-Cu interconnections is illustrated below with three technologies being concurrently pursued. The first research theme is the development of baseline assembly processes on ultra-thin glass substrates focused on high-speed thermocompression bonding, and applying it for center-wide design and demonstration test vehicles. The second research focus is on extending the applicability of solders by forming all-IMC interconnections formed by metastable SLID bonding to achieve improved power handling capability, thermal stability and pitch scalability. The last research theme focuses on the development of manufacturable all-Cu interconnections bringing innovations in materials and structures to achieve metallurgical bonding at temperatures below 200°C and pressure below 40MPa with short cycle times.​

Chip-level I&A program strategy.

Board-level Chip-level Interconnections Assembly and Reliability (BLIAR)

Board-level interconnections face two main challenges: package-to-board pitch and increased stress as the high-density interposers are developed with low-CTE substrates and as their size is increased from small  wafer-level packages to ultra-large interposers that are as big as 50mm in size. GT PRC proposes glass as a new substrate platform for a wide range of applications. Due to its high modulus, glass substrates exhibit lesser warpage than organics which enables direct glass package-to-board SMT assembly with larger body sizes. This unique approach is illustrated below. The board-level I&A program aims at: 1) understanding the limitations of applicability of standard SMT technologies to glass packages in body size and BGA pitch; and 2) explore, develop and demonstrate innovative low-cost, SMT-compatible stress-management approaches to meet emerging needs beyond traditional solders, enabling system-level reliability at pitches below 400µm without underfill.

Board-level interconnection trends and GT PRC’s R&D focus.

The strategy of the board-level I&A program is to explore, develop and demonstrate enhanced interconnection materials such as stress-relief interfaces, solders and underfills to meet emerging application needs, as illustrated below. The proposed strategy enables further system integration and miniaturization by addressing challenges of large body size and enabling pitch reduction. The R&D focus is on innovative doped solders to balance thermomechanical and drop-test reliability and reworkable underfills, in addition to introducing new compliant interconnection concepts beyond solder-based approaches.

 Board-level I&A program strategy: stress-relief mechanisms​.

For more information about the Interconnections & Assembly Research at GT PRC, please contact Dr. Vanessa Smet, Program Manager, at vanessa.smet@prc.gatech.edu.