PRC Vision

System Scaling for Smart Mobile, Wearable, IOTs, Bio-electrics, High-performance and Automotive Systems


Transistor scaling, starting with the invention of transistor in 1949, made electronics the largest single, $1.5T global industry, serving a variety of individual industries that span computing, communications, consumer, automotive and others. The basis for this industry is a result of singular focus in transistor scaling, leading to a 5B transistor chip, involving dozens of semiconductor, component and systems companies around the globe. But the electronics landscape has begun to change dramatically since 2007, driven by a new industry that integrates all these individual industries into so-called “Smart Mobile and Wearable Systems” that promise to perform every imaginable function, as shown in Figs. 1(a), (b), and (c), in smallest size and lowest cost that every global person could afford. Such a new frontier, however, requires revolutionary technologies referred to as System Scaling, in addition to transistor scaling during the last 60 years as shown in Fig. 2 which illustrates the gap between Transistor Scaling and System Scaling. Smart mobile systems are expected to drive unparalleled electronics hardware and software technology paradigms in system miniaturization, functionality, and cost. The system scaling technologies are many that need to be explored, developed, integrated, interconnected, tested and commercialized.

This is the technical vision of Georgia Tech PRC.

Fig. 1(a). Smartphone functions.

Fig. 1(b). Wearable systems functions.

Fig. 1(c). Smartphones are the new electronics drivers for ICs from 2012 to 2016.

Transistor Scaling and System Scaling Gap

Fig. 2 illustrates the advances in transistor scaling vs. system scaling during the last four decades, as measured by nodes and off-chip interconnections. The advances in the former is about 1000X, from 14 micron BEOL node in 1970 to 14nm, currently, in contrast to 5-10X in the latter from 500 micron off chip- I/O pitch to about 80 micron pitch, during the same time.

This gap is the basis for system scaling vision of the PRC.

The new system scaling technologies include new hardware architectures with particular focus in electrical, mechanical and thermal designs; new system substrate materials and processes; integration of ultra-thin actives and ultra-thin passives; miniaturized and innovative thermal structures; thinfilm power storages such as batteries; and interconnections between all of these at chip-level and board-levels. These will perform a variety of circuits and system functions that range from digital, analog, RF, wireless sensors, healthcare, power, bio, MEMS and network sensors. The functional focus in hardware, therefore must include:

  • Wireless electronicsFig. 2. Gap between transistor scaling and system scaling (courtesy Dr. S. Iyer, IBM)
  • Healthcare electronics
  • Wearable electronics
  • Sensor electronics
  • Camera electronics
  • 5FG RF / mm wave
  • Digital electronics
  • MEMS and sensors packaging
  • Photonics
  • Analog electronics
  • Power electronics

Limits with Organic and Silicon Packaging Technologies

Smart Mobile systems have two types of components: Devices and system components. Current hardware approaches involve packaging of individual ICs that range from processors, memory, RF, MEMS and sensors as well as passive components and batteries. While some of these are packaged as MCMs and 3D wire-bonded and stacked packages, there is very little system scaling. As such, mobile system companies see a limit to functionality driven by the thickness limit of about 6000 microns. This limit can be largely eliminated by changing from singular  current focus in transistor scaling to new system scaling and changing from the current organic hardware platform which presents four main limitations that include: 1) lithographic ground rules below 5 µm and bump pitch below 40µm, 2) thermal performance, 3) mismatch in TCE-driven, and moisture-driven reliabilities, and 4) warpage, as these organic packages are processed as ultra-thin packages at or above glass transition temperature. The lithographic ground rule limitation is due to the visco-elastic nature of polymers and thus is limited to about a 40µm pitch area array. The thermal conductivity of polymers is about three orders of magnitude less than silicon. The mismatch in TCE between Si and organic materials is huge, thus creating stresses on both the interconnections and the ultra-low-k on-chip dielectrics. The warpage is due to many factors including high TCE and low modulus.

Silicon substrates address most of the above challenges but they have two shortcomings: 1) low electrical performance due to high electrical loss, low resistivity and high dielectric constant, and 2) high cost primarily due to small 300 mm wafer size from which they are fabricated.

Panel-Based Glass 2.5D and 3D System Interposer Substrates

Glass appears to be the ideal candidate, as shown in Fig 3(a). As such it is being developed by Georgia Tech and its 50 member companies to address the shortcomings of both organic packages and silicon interposers. Fig. 3(b) clearly illustrates that any smart systems packaging must be panel-based so as to maintain ultra-low cost in spite of ultra-high I/O density.

Fig. 3(a). Glass as an ideal material for device and system packaging.Fig. 3(b). Panel-based glass packaging for low cost.