Systems Packaging Classes – Designed and Taught by Prof. Tummala

Since Systems packaging is inter-disciplinary which involves many faculty, many courses are taught at undergraduate and graduate levels, as described below.

Packaging Classes designed and taught by Prof. Rao Tummala, include:

Design-Build-Operate (DBO I) – Electronics Packaging Substrate Fabrication
ECE 4755 (Cross listed with ME and MSE) – Fall Semester  

The Design-Build-Operate (DBO) program is a unique educational activity initiated by PRC with support from the National Science Foundation (NSF). This one-of-a-kind program introduces undergraduate seniors and first year graduate students to the latest technologies in micro and nano-system substrates in within-substrate wiring and interconnections. Taught in world-class clean room prototype laboratories, the hands-on experience with the complete cycle of electronics systems manufacturing processes will prepare students for R&D, engineering, or manufacturing technology jobs in semiconductor and systems companies. This industry-centric, multi-disciplinary learning environment with its practical orientation to design, materials and fabrication processes, IC assembly and reliability testing provides Georgia Tech students with a head start to their careers in top global companies.

The course is spread over 12 weeks of intensive hands-on practice.

The entire program is offered in two semesters one that begins in the Fall and the second in the Spring. The DBO 1 course offered in Fall for ECE, ME, MSE and ChBE students, covers electronics packaging substrate fabrication processes and includes lectures and hands-on labs in the following topics:

  • Introduction to 3D Systems Packaging
  • Interconnect & Substrate Design Layout
  • Advanced Polymer Materials used for Next Generation Substrates
  • Dielectric / Polymer deposition and curing
  • Laser and photo processes for microvia formation
  • Fine line lithography process methods
  • Fine Line and Microvia Copper metallization
  • Multilayer wiring and build-up substrate technology
  • Embedded passives – capacitors, inductors, resistors
  • Inspection, metrology and substrate testing
  • Laboratory Safety

Design-Build-Operate (DBO II) – Electronic Packaging Module Assembly
ECE 4754 (Cross listed with MSE and ME) – Spring Semester  

This course focuses a current and next generation electronics packaging technology emphasizing hands-on experiences with electronics manufacturing processes, material systems, testing, and reliability assessment. Basic objectives are to gain a practical and fundamental experience in electronics module assembly, thermo-mechanical reliability, electrical functional test, and thermal management.

The course is spread over 12 weeks of intensive hands-on practice.

The Design-Build-Operate (DBO) program is a unique educational activity initiated by PRC with support from the National Science Foundation (NSF). This one-of-a-kind program introduces seniors and first year graduate students to the latest technologies in micro and nano-systems packaging. Taught in world-class prototype clean-room laboratories, the hands-on experience with the complete cycle of electronics systems manufacturing processes prepares students for R&D, engineering and manufacturing jobs in semiconductor, packaging and systems companies. This industry-centric, multi-disciplinary learning environment with its practical orientation to electrical and mechanical design, materials & fabrication processes, IC assembly and reliability testing provides Georgia tech students with a head-start to their careers in top global companies.

The entire program is offered in two semesters; one in the Fall and the second in the Spring. The DBO 2 course offered in Spring for ECE, MSE and ME students, covers electronics packaging assembly and reliability processes including the following lectures and hands-on fabrication and assembly topics:

  • Introduction to 3D systems packaging
  • Thermo-mechanical modeling and design
  • Interconnection, assembly and encapsulation materials
  • Materials characterization
  • Flip-chip assembly
  • Non-destructive inspection
  • Failure analysis
  • Laboratory safety

Introduction to SOP, SOC, SIP, 3D ICs and 3D Systems – An Interdisciplinary Electronic System Perspective
ECE 6776 (Cross listed with MSE and ME) – Fall Semester  

This course focuses on current and next generation systems.

This is a system level overview and a cross-disciplinary microsystems packaging course that introduces the new and advanced systems packaging technology concepts that have been explored and developed during the last decade for highly-miniaturized convergent electronic and bio-electronic systems for smart consumer, computer, telecom, wireless, healthcare and automotive systems. The course integrates various disciplines including electrical, materials, chemical, mechanical and bio- engineering to form the basis of new concepts that include SOP, SIP, 3DICs and 3D Systems. Within SOP and 3D Systems, it introduces digital, RF, optical and thermal SOP technologies.

This course is intended for graduate students in ECE, ME, MSE, ChemE, Physics and Chemistry. It provides both fundamental and applied aspects of digital and bio-convergent system technologies based on 15 years of intense research advances at the Microsystems Packaging Research Center at Georgia Tech by 35 faculty, 500 graduate students and more than 100 electronic companies. This course will be taught by multiple faculty and some industry experts in their area of expertise.

  • Technologies and their applications.
  • Explain what is meant by SOP, SOC, SOB, SIP, MCM, 3D ICs and 3D Systems and why miniaturize components and systems.
  • Explain two basic laws: Moore’s Law for transistor scaling ICs and Systems scaling for Systems
  • Explain, compare and contrast the 7 key microsystems technologies: SOB, SOC, MCM, SIP, 3D, SOP, and 3D Systems 
  • Explain the implications of SOP and 3D technologies for digital convergence.
  • Explain the role of such disciplines as ECE, ME, ChE, MSE in SOP R&D & Manufacturing, as well as in job careers in the industry.
  • Focus on and review SOP technologies: Mixed signal design, Digital SOP, Thermal SOP, RF SOP, MEMS SOP, Opto SOP, Bio SOP, WL SOP each involving organic or inorganic substrates thin film components, interconnections at IC and system level, and their reliability.
  • Explain future of SOP, such all-Si based 3D ASSM, as a potential disruptive technology.
  • Prepare students for industry culture by team work, interdisciplinary, selection of an R&D topic to write and present a term paper with individual contributions

If you have any questions regarding the above classes, please contact Ms. Karen May, Prof. Tummala’s assistant at karen.may@prc.gatech.edu .

Click here to see the comprehensive list of Systems Packaging Classes Taught at Georgia Tech