May 18, 2018 | Atlanta, GA
Power input and thermal outputs are two of the biggest challenges in all electronics. The need for thermal management arises because of the power supplied to the small ICs with highest electrical resistance in any system, according to the well-known Joule’s Law. Mobile products are trending to higher and higher performance, requiring thermal management in thinnest form factors and at lowest cost. In high-performance computing, increasing bandwidth requirements keep driving the need for 2.5D and 3D integrations with highest I/O densities and shortest interconnect lengths. But these integrations, particularly the 3D logic-memory package integration, presents new thermal management challenges that have yet to be fully addressed. In parallel, advances in electric cars enabled by the fast adoption of wide bandgap devices are driving the need for higher thermal and power densities, which requires novel integrated and miniaturized system-level cooling solutions.
Glass packaging is emerging as an ideal next-generation packaging substrate in 2.5D and 3D package architectures in high-performance computing and 5G communications because of its many advantages including ultra-high electrical resistivity, low loss, high thermal and dimensional stabilities and large-area panel manufacturing for low cost. Two package architectures are being concurrently pursued: substrate-based and embedding-based, both in large panels. However, glass has a relatively low thermal conductivity (~1 W/m∙K) compared to silicon (~150 W/m∙K), which may aggravate thermal challenges in some applications.
The Georgia Tech-led team is comprehensively addressing the above challenges with advances in all aspects of thermal management at chip and system levels, as shown in Figure 1, with: a) copper through-via structures and two-phase heat-spreaders, b) Near-zero and low-resistance thermal interfaces and c) external cooling with miniaturized single and two-phase cold plates.
The first step in solving the thermal challenge of glass substrates is to increase their thermal conductivity overall and at selective spots through inclusions of metalized copper structures.
- Copper through-package vias and two-phase heat-spreaders: Georgia Tech proposes and demonstrates a novel substrate cooling approach to overcome the limitations associated with low thermal conductivity of glass by incorporating copper structures such as through-package-vias (TPVs) and copper slugs, and copper traces in redistribution layers (RDL) into glass substrates and integrating ultra-thin (< 1 mm) two-phase heat spreaders (vapor chambers) which can spread heat more efficiently than copper into the mother board as shown in Fig. 2a. Through extensive modeling, fabrication and characterization, the thermal performance of glass interposers has been demonstrated closer to that of silicon as more of the above copper structures are introduced into the interposers. In addition, both interposers show almost identical performance after integration with vapor chambers as shown in Fig. 2b. The vapor chambers, which improve heat spreading by ~ 25% compared to thin copper RDL layers, offer significant thermal performance enhancements to glass interposers when coupled with thermal paths made of copper structures.
(a) schematic of glass interposer package with copper structures and vapor chamber integrated in PCB;
(b) junction-to-board thermal resistance in 4 different study cases; and
(c) thermal resistance of PCB integrated with vapor chamber (total thickness: ~ 1 mm) vs. copper plated PCB (total thickness: ~ 1 mm)
- Thermal Interface Materials (TIMs): The Georgia Tech team has also developed next-generation Thermal Interface Materials (TIMs) for both embedded and substrate-based packages, aiming at reducing the thermal contact resistances to provide maximum heat transfer from the chip. In embedded packages, the approach used involves direct-plated copper on chip, resulting in near-zero thermal interface resistance. In chip-last substrate-based packages, an innovative sintering approach to form thin interfaces is proposed and developed to realize all-Cu die-attach joints with minimum contact resistance, and highest thermal and electrical conductivities, to meet the emerging needs of analog and power systems.
- Zero-resistance TIM: Thermal dissipation requirements of 30-100W power amplifiers was addressed by integrating large copper heat spreaders directly and conformally onto the Si ICs, as shown in Fig. 3. By reducing the number of interfaces between the heat source and heat sink, heat transfer has been maximized. This innovative process was developed to achieve panel-scale direct metallization as well.
- Low-resistance TIM: Nanocopper sintered films were demonstrated with standard semi-additive processes of electroplating and chemical etching. The fabrication process is very versatile and can be used to form patterned-foam films on the die or substrate or as standalone foam films to be used as die-attach inserts. This technology, therefore, provides an innovative, manufacturable and cost-effective way to fabricate all-Cu, large-area die-attach joints to enable higher current densities and operating temperatures in emerging digital and analog applications, as well as provide a low-cost alternative to Ag- sintering in power electronics systems. Film sintering at 200°C directly to Cu metallization was demonstrated, forming strong and reliable joints with bulk-like Cu properties, as shown in Fig. 4.
- Miniaturized liquid-cooling: The Georgia Tech team also addresses the miniaturization challenges in system-level cooling with a new class of integrated cold plates. The use of customized, additively- manufactured metal foams, as shown in Fig. 5, is developed to improve thermal performance by using the advanced metal foams (high specific surface area, thermal conductivity, and specific volume) to improve temperature uniformity, to manage hot spots, and to create additional nucleation sites for liquid boiling and enable, for the first time, reliable two-phase cooling. Additive manufacturing provides design flexibility in realizing customized foam inserts, providing a comprehensive solution for miniaturization of system-level liquid cooling.
(a) thermal resistance of PCB integrated with vapor chamber (total thickness: ~ 1 mm) vs. copper plated PCB (total thickness: ~ 1 mm).
(b) composite metal foams.
About the Authors
Dr. Sangbeom Cho was a PhD student in PRC, and advised by Prof. Yogendra Joshi and Prof.Tummala. His research focus is on thermal modeling, design and characterization. He is currently with Qualcomm and can be reached at email@example.com
Nithin Nedumthakady is a PhD student in Prof. Rao Tummala’s group, and being mentored by Dr. Venky Sundaram and Dr. Vanessa Smet. His research focus is on thermal management in embedded modules, firstname.lastname@example.org.
Kashyap Mohan is a PhD student in Prof. Rao Tummala’s group, and being mentored by Dr. Vanessa Smet. His research focus is on nano-copper die-attach materials, email@example.com.
Justin Broughton is a PhD student in PRC, and advised by Prof. Yogendra Joshi and Prof Tummala. His research focus is on thermal modeling, design and characterization, firstname.lastname@example.org
Dr. Venky Sundaram is a Research Professor in Prof. Tummala’s group, and the Deputy Director of the Center, email@example.com.
Dr. Vanessa Smet is a Research Professor in Prof. Tummala’s group, and the Program Manager for high-power packaging, thermal management and interconnections and assembly areas, firstname.lastname@example.org.
Prof. Yogendra Joshi is an Endowed Chair Professor in the ME Department, Georgia Tech. email@example.com.
Prof. Rao Tummala is the Joseph M. Pettit Chair Professor in ECE and MSE, and the Director of Georgia Tech’s 3D Systems Packaging Research Center (GT PRC), firstname.lastname@example.org.