Greetings! Welcome to the PRC Quarterly Newsletter.
Since our last newsletter so much has changed. Due to COVID-19, Georgia Tech imposed a lockdown starting Mar 30, 2020 requiring that all classroom instructions and non-essential laboratories be closed. Georgia Tech moved to distance learning for the remaining part of spring semester. A similar story has been playing out around the rest of the globe. These are difficult times and we pray for the well-being of one and all on planet earth as we get through this crisis.
We at PRC have continued to make progress in research in spite of our laboratories being shut down thanks to the creativity, perseverance, determination and resilience of our students, staff and faculty. Over the last month, several students have made progress towards their graduation requirements be it thesis defense or proposal exam, our engagement with industry members has increased manifold, and our publications continue to be on the rise. While we vigorously prepare for our first virtual industry advisory board meeting in May 2020, we continue to brainstorm on new ways by which we can bring value to our members, collaborators and programs.
The semiconductor industry is betting on heterogeneous integration (HI) as the path forward. This is being driven primarily by artificial intelligence in the automotive, industrial and communication sectors. Such a trend is driving the packaging research at PRC leading to investment in four areas namely, high performance computing (HPC), power delivery (computing & automotive), wireless (5G & beyond) and emerging technologies, consistent with the 2019 Heterogeneous Integration Roadmap (HIR). We believe that convergence of these applications on a System on Package (SoP) platform using a multitude of chips (2.5D & 3D assembled & embedded) from multiple domains on a single substrate with high density wiring and passives will dictate future research needs. If you are interested in learning more about our research portfolio please do not hesitate to contact us.
We provide below some recent research highlights in this newsletter.
Co-integration of Electronics and Photonics using BCB Polymer
With the trend towards heterogeneous integration, the need for co-integrating photonics and electronics into a single substrate becomes necessary. PRC has investigated using BCB polymers to enable this integration. Single mode polymer waveguides (SMWG) for high bandwidth communications and embedded trenches for high speed electronics have been developed and demonstrated using the same polymer material (BCB) on glass interposers. Polymer SMWGs on glass suitable for direct fiber coupling have been designed and demonstrated. For interconnections, 3 µm dielectric trenches were achieved for supporting ultra-fine copper traces with 2 µm microvias fabricated on the same dielectric film. This work was recently published by graduate student R. Zhang with co-authors F. Liu, M. Kathaperumal, M. Swaminathan, and R. R. Tummala in the IEEE CPMT Transactions titled, “Co-integration of Single-Mode Waveguides and Embedded Electrical Interconnects for High-Bandwidth Communications”, Vol 10, No. 3, 393-399, 2020. Read More.
Top view of dielectric (BCB) lines and trenches (Left) and 2, 3, 4 µm microvias with 4, 6, 8 µm pitch respectively before Cu plating (Right).
Integrated Voltage Regulators with Embedded Inductors
High efficiency and high conversion ratio Integrated Voltage Regulators (IVR) require embedded inductors. We have recently developed a novel expandable interleaved toroidal inductor using magnetic core and vias that can be integrated into substrates. The first demonstration of these fabricated inductors show an inductance density of 77nH/mm3 using the magnetic material from Panasonic. This work was jointly supported through ASCENT (JUMP Center) and Packaging Research Center (PRC). Details of this research will be presented at ECTC ’20 by graduate student C. Alvarez along with his co-authors from Georgia Tech: S. Suresh, M. Swaminathan, R. Tummala and Panasonic: D. Sasaki, K. Watanabe, R. Nagatsuka, C. P. Lin, T. Wada and N. Watanabe.
Integrated Voltage Regulators (Top Left), Toroidal Inductor Topology (Bottom Left) and Fabricated Inductor (Right)
Physically Consistent Neural Networks for Electrical Design
Design of chip-to-chip connections for Heterogeneous Integration require accurate predictive electrical models, which can be generated using neural networks (NN). A fundamental drawback of NN based models is that they are “non-physical”, meaning that NN predictions can violate the underlying physical phenomena represented by the data. Hence generating broadband S-Parameters using NN where the predictions obey physical constraints such as causality and passivity become problematic. This has been addressed by developing a physically consistent NN architecture consisting of causality enforcement layer (CEL) and passivity enforcement layer (PEL). When applied to differential plated through hole (PTH) pair in package core, the results showed that the predicted S-Parameters are 100.0% causal and passive, while providing similar accuracy as non-physical NNs. Details of this work supported by the Center for Advanced Electronics Through Machine Learning (CAEML) and co-authored by H. M. Torun, M. Swaminathan (PRC) and A. Durgun, K. Aygun(Intel) was presented at EPEPS’19. Read More.
Physically Consistent Neural Network (Top) and predicted Broad-band S-parameters (Bottom)
Antenna in Package Integration
5G Antenna-in-Package (AiP) require power dividers to feed antenna arrays. Recent work has shown that package-integrated power dividers with small footprint at 28 GHz is possible by utilizing precision low loss redistribution layers (RDL) on glass substrates. Two conﬁgurations of power dividers with two-way and three-way equal power split have been modeled, designed and fabricated on glass substrates with thin-ﬁlm build-up layers. This approach combines the beneﬁts of ceramic and low-loss polymers for performance, while providing silicon-like dimensional stability of glass for precision panel-scale patterning. This work was presented at IEEE ECTC ‘19 by graduate student M. Ali with co-authors R. Tummala, A. Watanabe, T. Lin, Prof. M. R. Pulugurtha, and M. Tentzeris. Read More.
Glass Interposer (Left), 2×1 Yagi-Uda antenna array: Design & Fabrication (Middle) and Simulated/Measured radiation pattern of 2×1 Yagi-Uda antenna array
Dr. Vanessa Smet recently joined the George W. Woodruff School of Mechanical Engineering
at Georgia Tech as an Assistant Professor. After a two-year postdoc at Tyndall National Institute
(Cork, Ireland), Vanessa joined the PRC team in late 2012 as a Research Engineer where she
focused her research on advancing interconnection and assembly technologies as well as
exploring novel 3D architectures for the packaging of wide-band gap-based power electronics
in electrified transportation. Her research interests span from the design, characterization, and
fabrication of metals and metal-based composites at the micro- to nano-scales to meet application-
driven performance and manufacturing criteria; integrated and miniaturized cooling solutions; multi-
physics modeling and design optimization; and reliability, prognostic and condition monitoring.
In her new role, Vanessa will continue to provide leadership in these research areas as part of the
PRC team and is delighted at this opportunity to educate more of our School's students on electronic
packaging as a highly interdisciplinary science.
Siddharth Ravichandran received the 2020 IEEE Electronics Packaging Society (EPS) Ph.D.
Fellowship award for demonstrating exceptional ability to perform independent research in
the field of electronic packaging and for his contributions to the development of 2.5D and 3D
Glass packages for heterogeneous integration in high-performance computing (HPC). His
research is on designing and demonstrating a novel 3D packaging architecture using glass-
based panel embedding to achieve superior bandwidth and power-efficiency than current
state-of-the-art Silicon interposer packages at low-cost and high thermo-mechanical reliability.
Siddharth started his Ph.D program in the School of Electrical & Computer (ECE) Engineering
supported by the PRC in 2017. He received his M.S. in ECE from Rutgers University, New
Jersey in 2016 and B.S. in ECE from College of Engineering - Guindy, Chennai, India in 2013.
Details of the award are at: https://eps.ieee.org/awards/phd-fellowship.html.
Congratulations to our 2020 Graduates!
Shreya Dwarakanath, Ph.D.
Srinidhi Suresh, M.S
PRC IAB Virtual Review Meeting: May 19-21, 2020
IAB Session I
Taiwan - May 20, 2020, 8:00 - 11:00 AM Taipei Standard Time
Japan & Korea - May 20, 2020, 9:00 AM - 12:00 PM JST & KST
North America - May 20, 2020, 10:30 AM - 1:30 PM ET
May 20, 2020, 7:30 - 10:30 AM PT
Europe - May 20, 2020, 4:30 - 7:30 PM CEST
IAB Session II
Taiwan - May 21, 2020, 8:00 - 10:30 AM Taipei Standard Time
Japan & Korea - May 21, 2020, 9:00 - 11:30 AM, JST & KST
North America - May 21, 2020, 10:30 AM - 1:00 PM ET
May 21, 2020, 7:30 - 10:00 AM PT
Europe - May 21, 2020, 4:30 - 7:00 PM CEST
All PRC members are invited to join. If you are with a non-member company and would like to attend and learn more about PRC, please do not hesitate to contact us.
ECTC: June 3-30, 2020, Virtual Platform