The Georgia Tech Packaging Research Center is pioneering ultra-high I/O density glass BGA packages as the next generation, beyond Si interposers that are used in all high-end applications, for four reasons.
- Superior electrical properties for performance and power;
- Larger area processing for lower cost;
- Lower resistance for larger packages;
- Optimized TCE for both IC and board-level reliability without the need for another BGA package;
Superior Electrical Properties: Georgia Tech’s glass interposer approach achieves superior electrical performance compared to silicon interposers because of lower electrical loss, lower line resistance, smoother surface finish, lower dielectric constant and ultra-high insulation resistance. (Figure 2). The dielectric constant of glass is 5.3, about half of the dielectric constant for silicon. The electrical loss of glass is 0.005 compared to Si of 0.015, about 30X better than Si. The resistivity of glass is 1013 Ω*m compared to 0.1 Ω*m. Glass also provides a path for running signals at much longer distances due to the inherent benefits that glass provides over silicon. The electrical loss of the build-up dielectrics utilized in Georgia Tech’s glass BGAs are much lower, providing unmatched benefits in electrical performance. Glass is the only package capable of simultaneously supporting 1000 channels at 1Gbps, and also high-speed channels at 29 and 56 Gbps for SERDES or other external I/Os.
Larger area processing for low cost: Georgia Tech’s approach to glass is panel-based, about 510 mm in size, compared to Si that is 300 mm, wafer–based. Georgia Tech believes that packages from 300 mm wafers are not cost-effective beyond 15mm in size, for except very high-end applications. To demonstrate cost-effective panel-based packages, Georgia Tech is pioneering next-generation of ultra-low loss and ultra-thin materials, tools, and processes to 1 micron RDL lithography. Georgia Tech is demonstrating a path to fabricating high-density packages with panel-scalable processes, with up to 510 mm panels in the short term, and even larger panels in the long-term. This switch from small wafers to large panels ultimately lowers the cost by >5X, but requires highest RDL yield, which is very difficult. Furthermore, silicon utilizes costly through-silicon-via (TSV) and single-side processes. Georgia Tech and its partners demonstrated low-cost, high throughput through-package via (TGV) processing with up to 10,000 vias/second. Double-side fabrication on glass with TPVs further lowers the cost.
Lower resistance for larger packages: Silicon BEOL processes typically achieve an aspect ratio of wiring in the range of 1 – 2x, which makes the line resistance 17Ω/mm. Georgia Tech’s next-generation process and materials can achieve sub 6Ω/mm with aspect ratios of 3 or higher (Figure 4). The combination of next-generation materials, and process makes Georgia Tech’s Glass Interposer technology the only option for high-density applications with large body sizes and low resistance.
Optimized TCE for both IC and Board-level reliability without the need for another BGA package: Glass also enables simultaneous chip- and board-level reliability without the need for an additional package (Figure 5). Silicon interposers are perfectly-matched to the Si IC’s, but totally mismatched to the board. To compensate for this mismatch, an additional organic BGA package is required, which increases thickness, size and cost, and degrades electrical performance. Glass can be selected with tailored-TCE anywhere between Si TCE and board TCE. As shown in Fig. 5, the GT team has modeled board-level reliability for large package sizes of >400mm2. The modeling work done by the GT team has shown that the best TCE for 2.5D Glass Interposer to be in the range of 7-10 ppm/C.
With major innovations in design, low-loss and fine-pitch RDL materials and processes, through vias, large-chip assembly to 20µm pitch and direct-attach of large package sizes to system board, without an intermediate package, GT and its partners have clearly established 2.5D glass interposer technology as a superior alternative to organic interposers in interconnect density, and silicon interposers in electrical performance, power consumption, and cost. The package is also designed to achieve high reliability at both chip- and board-levels. With continued panel RDL scaling, low-loss, high-speed die-to-die wide I/O, low-loss external I/O, GT is now extending 2.5D glass interposers to meet next-generation high-performance computing system requirements in terabit per second bandwidth applications.
This work is performed with Global Partnership that includes materials companies, tool companies, substrate companies and assembly companies, with end-user companies driving the technology forward to commercialization.
About the Authors
Bartlet H DeProspo is a PhD student under the advisement of Prof. Rao Tummala. His research focus is on Design and Demonstration of 2.5 Glass Interposers.firstname.lastname@example.org.
Prof. Rao Tummala is the Joseph M. Pettit Chair Professor in ECE and MSE, and the Director of Georgia Tech’s 3D Systems Packaging Research Center (GT PRC). email@example.com.
Dr. Venky Sundaram is the Deputy Director, Research Professor and the Program Manager of Glass Substrate Program at GT PRC firstname.lastname@example.org.