Georgia Tech develops industry’s first panel level packaging to the same characteristics as wafer- based BEOL with a novel damascene- like via-in-trench (ViT) interconnect redistribution layer (RDL) technology. This damascene RDL technology comprises of ultra-fine copper embedded trenches and microvias with diameter equal to the width of trenches using a 5 µm thick dry- film photosensitive dielectric. A 140 µm thick glass substrate is used as the core material. The new ViT interconnect technology is targeted for next generation of 2D, 2.5D and 3D interposers and packages with highest I/O density. The ViT RDL is integrated with 2 µm diameter microvias with 2.5 µm half-line pitch copper traces embedded in a 5 µm thick dry film photo-imageable dielectric (PID) polymer. This new RDL technology directly translates to IO density of 200 IO/mm/layer. IO/mm/layer, as defined by Intel, is the number of wires routed per mm of die edge on each layer of package substrate. There is no capture pad required for Georgia Tech’s ViT. The routing Cu traces are aligned directly on top of microvias instead of the conventional via-capture pad-trace interconnect configuration. The fabrication of such a high density RDL is achieved by patterning a trench over via and then fully filling with plated copper. Conventional i-line (365 nm) photolithography, widely used for patterning PWB and package substrates, was employed to form small trenches as well as small microvias in the PID. An advanced 5 μm thick PID film IF4605 was selected for build-up layers. Experimental results showed that microvias with diameters of 2 μm and trenches with half-line pitch of 2.5 μm were achieved in a 5 μm thick IF dry film. Traces with half-line pitch of 1 μm were also demonstrated in a 3 μm thick liquid photo resist film. The aspect ratios were 2.5 for dry film PID and 3 for liquid photo-resist respectively. The best interconnection density as defined by IO/mm/layer was calculated to be 200 using dry film PID and can be extended to 450 using thinner PIDs. For comparison, the IO density of the state-of-the-art organic interposers are typically around 40 using semi-additive processes (SAP). The new embedded trench technology breaks the limit of current SAP to achieve 5-10X improvement in interconnect density, compared to SAP. The ViT interconnect technology is a revolutionary panel-size RDL technology that allows panel packaging to reach wafer based RDL characteristics for the first time to dramatically improve I/O density to improve cloud computing bandwidth.
Fuhan Liu, Chandrasekharan Nair, Atsushi Kubo, Tomoyuki Ando, Hao Lu, Rui Zhang, Hang Chen, Kwon Sang Lee, Venky Sundaram, Prof. Rao R. Tummala. Fuhan Liu and his co-authors won an outstanding interactive paper award at IEEE ECTC 2017 for this work.