Clearly the world is moving towards systems enabled by artificial intelligence (AI) and therefore we believe that this represents a major driver for system integration. The expected market size for automotive, industrial and mobile segments based on neuromorphic sensing and computing projected over the next 15 years is shown in Figure 1, which represents a sizeable opportunity. If one focuses on traditional computing the use of CMOS, CPU and GPU devices and architectures is being limited by Moore’s law, memory wall, and heat wall, as shown in Figure 1 and therefore neuromorphic sensing and computing with better memory access is required.This is the technical vision of Georgia Tech PRC.
Figure 1: Need for neuromorphic sensing & computing & Emerging Market Size (Courtesy: Yole Development)
An example of continuous learning from the environment using neuro-evolution in hardware, which requires learning at the edge in the absence of a (i) pre-trained Deep Neural Network (DNN) (ii) labeled data sets and (iii) connectivity to a backend cloud server due to latency, is shown in Figure 2. For such emerging applications a requirement is to evolve the DNN topology continuously in response to rewards using evolutionary algorithms that requires 2 to 5 orders more energy efficiency than CPUs and GPUs. For such architectures data movement with low energy per bit (EPB) and high bandwidth density becomes essential. Data movement can be separated into two major parts namely, i) over long distances where interaction and data collection from the environment becomes critical where wireless technologies are required and ii) over short distances that support energy efficient computing, as shown in Figure 2.
Figure 2: Need for neuro-evolution in hardware at the edge (Courtesy: T. Krishna, GT)
A system architecture that combines wireless and computing functionality on a single platform is shown in Figure 3, which consists of multiple chiplets interconnected together on an integrated substrate. The chiplets come from multiple domains that include logic, high bandwidth memory (HBM), radio frequency (RF), photonics (PIC) and sensing/actuation. The chiplets are tightly integrated, support high performance computing (HPC) that combines CPU, GPU and ACC (Accelerators), have integrated power delivery and management and interact with the environment through broadband 5G and beyond 5G (6G) wireless connectivity. Such a convergent System on Package (SoP) module would have chips interconnected using 2.5D and 3D connections through short distance, massively parallel (Cu) interconnects for digital communication using beyond CMOS devices, embedded III-V dies (die in cavity) for RF amplifiers, photonic interconnects in module for SerDes using silicon photonics (PIC), switching regulators with GaN power FETs connected to embedded passives, antenna arrays (FEM), and thermal management solutions from all sides, to name a few. Such a futuristic heterogeneous SoP module is consistent with the IEEE Heterogeneous Integration Roadmap  which provides a vision for the electronics industry and identifies future challenges and potential solutions that relate to packaging technologies. We believe that the SoP approach would lead to enhanced functionality and improved operating characteristics, as compared to either System on Chip (SoC) or using multiple levels of packaging practiced today.
Figure 3: System Architecture & Heterogeneous Integration
For many years, system integration was driven by System on Chip (SoC) technologies, leading to larger SoCs with scaled devices. With the move towards heterogeneous integration, we see a need for integration that goes far beyond Multi-chip modules (MCM), System in Package (SIP) and 3D Stacks and provides attributes not attainable with such technologies. Our vision is therefore to develop the next generation of SoP technologies that merge the package and board together, contain embedded functionality covering multiple signaling domains, provides a seamless interface to SoC that can be assembled on both sides or embedded in the package and is highly reliable, as shown in Figure 4. We see such a heterogeneously integrated system module as a means to continue Moore’s law.
Figure 4 System on Package (SOP)
 2019 Heterogeneous Integration Roadmap (HIR) https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2019-edition.html