Glass Substrate (Electronic) Research

Glass Substrate (Electronic) Vision & Strategy 

The vision of the substrate program is to explore and demonstrate the most leading edge substrate technologies with highest I/O density, highest performance and reliability at lowest cost in a variety of substrate architectures that include single-chip, multi-chip in 2.5D and in double-side 3D with both electronic and photonic interconnections. Such substrates are targeted for a broad spectrum of applications from smart mobile logic, high performance logic-to-memory integration, memory sub-system integration, high performance computing, RF, analog, and high speed networks.

Glass Substrate Strategy

The historical trend from ceramic to current organic packages is plotted as a function of cost/mm2, and I/O pitch, as the two most important package metrics. Although silicon interposers address the I/O pitch scaling, they do not meet the cost targets for most applications, and this is the basis of the Low-cost Glass Interposer and Package (LGIP) industry program at GT PRC.

GT PRC strategy: Panel-based Glass Interposers & Packages for I/Os and Cost​

The low-cost glass interposer technology at Georgia Tech PRC is being pursued for two primary reasons: 1) to provide alternatives to high cost wafer silicon interposers, 2) to extend the chip-level I/O pitch beyond organic packages that are currently at 80-120µm pitch to as low as 20-40µm pitch in the next two years.

Low-cost Glass Interposers and Packages (LGIP)

The objective of glass packaging in a variety of 2D, 2.5D and 3D architectures is to interconnect a variety of leading-edge ICs and 3D ICs, at the same wiring and I/O density as silicon interposers with TSVs, but at 5-10X lower in cost in high volume. The cost of glass is expected to be comparable to organic interposers but at smaller bump pitch.

Glass packaging started in a big way at Georgia Tech in 2010, to explore glass as a superior alternative to silicon Interposers because of its outstanding electrical resistivity, low loss and low dielectric constant, and its availability in ultra-thin and to roll-to-roll shapes to form low-cost, ultra-thin interposers from large area processing. As the Georgia Tech PRC team began to demonstrate such an interposer with its dozens of global industry partners addressing major barriers that include how to handle large, ultra-thin brittle glass panels, how to form large number of ultra-small through vias at small pitch, how to metalize these small copper vias without defects and with good adhesion, how to form 2-5µm multi-layer RDL wiring layers with bump pitch in the 20-50µm range, how to assemble chips to these brittle substrates and how to improve its thermal conductivity, it became clear that glass can be a pervasive platform technology that is both a high performance and very low cost technology.

Center-wide D&Ds based on Glass Substrates

Such Glass Substrates being developed at GT PRC, therefore, are not just ultra-high I/O interposer substrates, but a pervasive low-cost platform packaging technology that is suitable for packaging all devices including cost-sensitive MEMS and Sensors Packaging, RF, Power and Analog Packaging, and microprocessor packaging, as shown in Glass Substrate (Electronic) Program (LGIP). In addition, it is applicable and is being developed for packaging of 2.5D multi-chip packaging with ultra-high number of interconnections between chips in side-by-side configuration. Ultimately, they are being developed as a superior alternative to 3D ICs with through-silicon-via (TSV)-like dimensions in glass, in what is called 3D interposer packages.

For more information about Glass Substrate Research at GT PRC, please contact, Dr. Venky Sundaram, Program Manager at