Happy New Year! I hope you had an enjoyable holiday season.
Through this first quarterly newsletter for 2020, I share with you our progress over the last few months including our plans for the future. We had a terrific Industrial Advisory Board (IAB) meeting in Nov ’19 with a record turn-out of 140 attendees. As PRC expands to include several federally funded programs, we view our interaction with industry as being strategic. Hence, we continue to expand our industry collaboration by divulging into new research areas. In addition to Artificial Intelligence (AI), High Performance Computing (HPC), Power Electronics and mmWave applications we have now expanded into automotive electronics and have started investing in emerging technologies such as flexible electronics, organic packaging, integrated photonics and 3D integration. We continue to make significant progress in high density packaging, embedded magnetics/dielectrics, fine pitch assembly, and integrated thermal management solutions supported by machine learning based design approaches.
Fall ’19 was a busy time for me as I traveled the globe. One of these trips was especially noteworthy which I share here. In Sep ’19 I was invited to teach a half day tutorial on heterogeneous integration titled “Intelligent Digital Convergence for AI and 5G” in Penang and Kuala Lumpur, supported by the IEEE EPS Malaysia Chapter. The workshop was attended largely by millennials. It was an absolute pleasure to teach a tutorial to such a warm and vibrant audience who kept me on my toes with questions, comments, opinions and solutions. After the workshop, I came to the conclusion that the future of packaging is in good hands as us Baby Boomers and Gen X begin to look to the millennials to carry the torch forward.
Through this newsletter we share some of our research highlights and other activities. If you are interested in knowing more about the PRC or would like to collaborate, please do not hesitate to contact us.
- Madhavan Swaminathan, PRC Director
IEEE EPS Malaysia Chapter Workshop
November 2019 Industrial Advisory Board (IAB) Meeting
Glass Panel Process Scales to 1um dimensions with Low Resistance RDL
A major bottleneck for increasing logic to memory bandwidth and reducing energy consumption is scaling of the redistribution layers (RDL) on the interposer to 1um or less. This is possible through high aspect ratio interconnects that can maintain high densities while reducing resistance and latency. Although traditional approaches for reducing critical dimension (CD) are to leverage back-end-of-line (BEOL) technologies to reach on chip like dimensions, this approach is prone to high losses in the package. We have recently reported on advanced processes to fabricate low loss RDL interconnects with a CD of 1um using advanced photoresist materials, and a new scheme to overcome seed layer etching challenges. The advanced photoresist materials are available in liquid and dry film forms which are beneficial to achieve fine line dimensions. A processing method has been developed to overcome the seed layer scalability challenges. For the first time we have demonstrated that by using a different conductive seed metal than copper the photoresist can be placed onto the conductive seed layer with no degradation in photoresist performance for achieving a CD of 1 um. This work was presented at the 2019 ECTC conference in Las Vegas by Bartlet DeProspo along with co-authors A. Momozawa, A. Kubo, C. Nair, V. Rajagoapal, J. Kannan, E. Surillo, F. Liu, M. Kathaperumal and R. Tummala. Further details on the technology can be found here.
Glass Interposer Stack-up (left) and Cross Sectional Images of Photoconductive Dry Film & Liquid Resist on Copper and Chromium (right)
Power Delivery Design using Machine Learning
Designing power delivery networks can be complex due to the many resonances that can occur. A bandlimited response can sometimes lead to surprises since resonances may occur in the vicinity or outside the frequency region. Can a bandlimited response such as that of a power delivery network be extrapolated outside the frequency range over which it has been measured or simulated? This is the fundamental question we plan to answer through this research. As a preliminary solution we propose a machine learning based method using long short term memory recurrent neural networks (LSTM-RNN). Initial results show that the accuracy in the prediction is good with a mean square error of 0.008 where the response over a 12GHz bandwidth can be extrapolated by an additional 65%. Details of this work supported by the Center for Advanced Electronics through Machine Learning (CAEML) and co-authored by O. W. Bhatti and M. Swaminathan presented at EPEPS ‘19 can be found here.
Power Delivery Network (left), LSTM-RNN (center) and Extrapolated Impedance Response (right)
Advances in Glass based Packaging for 5G Applications
Unlike silicon interposers, glass interposers provide unique opportunities for mmWave packaging due to their low dielectric constant and low loss properties combined with good dimensional stability and smooth surfaces. We have recently demonstrated high-bandwidth fully-integrated antenna-in- package modules with low-loss interconnects from chip to antenna using glass-packaging technology. Low-loss dielectric thin-films on 100 μm glass core are utilized as the substrate with double-sided routing and interconnect layers. PhD student Atom Watanabe was recognized for this work with the ICEP IEEE CPMT Japan Chapter Young Engineer Award at the 2018 International Conference on Electronics Packaging (ICEP). The title of Atom’s award-winning paper was "Design and Demonstration of Ultra-thin 3D Glass-based 5G Modules with Low-loss Interconnects” with co-authors R. Tummala, T. Lin, T. Ogawa, P. M. Raj, V. Sundaram and M. Tentzeris. Details of the paper are available here.
Glass Based Packaging for 5G (left) and Insertion Loss of Transmissions Lines and Vias at 28GHz
Power Module Packaging
Power module packaging technologies have been experiencing extensive changes as the SiC power devices become commercially available. SiC devices provide for reduced power loss, higher switching frequency and high temperature operation as compared to silicon devices. As we expand into automotive electronics, we provide a review of the packaging challenges associated with high-speed switching, thermal management, high-temperature operation, and high voltage isolation for such applications through a recent paper authored by H. Lee, V. Smet and R. Tummala titled “A Review of SiC Power Module Packaging Technologies: Challenges, Advances, and Emerging Issues” published in the IEEE Journal of Emerging and Selected Topics in Power Electronics. We note that the trend towards novel soft switching power converters give rise to problems related to package design of unconventional module configurations. Details of the paper are available here.
Advances in Packaging Structures (left) and 3D Stacked Power Modules (right)
|Prof. Suresh K. Sitaraman was recently recognized with the 2019 Zeigler Outstanding
Educator Award. This award was created in 1999 to recognize an outstanding educator
among the academic faculty of the Woodruff School of Mechanical Engineering at Georgia
Tech. This is a lifetime achievement award that a person can receive just one time.
Prof. Sitaraman is a Regents’ Professor and a Morris M. Bryan, Jr. Professor in the George
W. Woodruff School of Mechanical Engineering at Georgia Tech. His research focuses on
micro- and nano-scale structure fabrication, testing and characterization as well as physics-
based modeling and reliable design, as applied to rigid and flexible microsystems. His work
has been recognized through recent awards and honors that include being named the NextFlex
Fellow in 2018, Outstanding Achievement in Research Program Development Award (Team
Leader) from Georgia ASME/EPPD Applied Mechanics Award in 2012 and the Thomas
French Achievement Award from the Department of Mechanical and Aerospace Engineering,
The Ohio State University in 2012.
|Shreya Dwarakanath will be joining Intel in Chandler, AZ in Spring ’20 after graduation with a PhD in
Materials Science and Engineering. Shreya’s research interests include inorganic-organic hybrid
polymers and interfaces, automotive electronics, and high-temperature reliability characterization. Her
current research looks at improving the interfacial adhesion between polymer dielectrics and metal
layers. She has given two oral presentations at IEEE Electronic Components and Technology
Conference (IEEE ECTC- 2017 & 2018) and several poster presentations. Shreya’s work has been
recognized with awards such as the Best Student Paper at International Microelectronics and
Packaging Symposium (IMAPS), and the best session for advanced electronics in 2016. She also
placed second in the poster competition for Future Car Electronics (FCE). Shreya received the Jewell
Fellowship for Fall 2018 based on her academic achievements and service to Georgia Tech. She was also
awarded the Scheller School of Business Dean’s Fellowship on merit basis to pursue a fully funded join
MBA at Georgia Tech. As an undergraduate, Shreya received the Ministry of Steel scholarship, which
supported three years of her tuition.
Congratulations to our 2019 Graduates!
Dr. Chandrasekhar S. Nair
Dr. Robert G. Spurney
Dr. Huan Yu
- JUMP ASCENT Workshop: February 24-25, 2020 @ Georgia Tech (Attendance by invitation only.)
- CAEML Review: April 28-29, 2020 @ Georgia Tech (Attendance by invitation only.)
- PRC IAB Review: May 21-22, 2020 @ Georgia Tech (Attendance by invitation only.)
- ECTC: May 26-29, 2020 @ Orlando, FL. Please visit the PRC booth at ECTC.