Greetings from the 3D Systems Packaging Research Center (PRC) @ Georgia Tech. As the new director of PRC, I would like to extend a warm welcome. I assumed the Director role in Mar ’19 and have been spending the last few months meeting with our industry collaborators, sponsors, faculty, staff and students. I had the opportunity to host my first Industrial Advisory Board meeting in May ’19 and had the pleasure of participating in the 25th Anniversary celebrations of PRC. I joined PRC in 1994 and witnessed the inauguration of the first NSF Engineering Research Center (ERC) @ GT namely the Packaging Research Center. So, celebrating my 25th anniversary along with PRC’s was the icing on the cake. PRC under the leadership of Prof. Rao Tummala has flourished and I hope to continue that trend. It is with utmost gratitude that we bid farewell to Prof. Tummala who will continue to serve in an advisory role to PRC.
Prior to becoming the Director of PRC, I was the Founding Director of the Center for Co-Design of Chip, Package, System (C3PS), a center that focused primarily on design with some effort on materials and process. We are now in the process of merging C3PS and PRC, leading to a mega-center on packaging that has significant expertise not just in materials and process but also in design and system integration. Our focus will continue to be on leading edge packaging but with the ability to integrate ICs and prototype functional systems. With the merger, the new PRC has a total of 20+ faculty from four different schools involved (ECE, MSE, ME and ChBE), 8 research staff, 50+ graduate students, 35 industry collaborators spanning the supply chain and several large multi-year programs. Our research is currently driven by application areas such as Artificial Intelligence (including High Performance Computing), power electronics (data centers & automotive) and mmwave (5G & 6G) with a focus on digital, RF and optical signaling for both rigid and flexible packaging.
Through this quarterly newsletter, we show case some of our recent research highlights and awards. We look forward to your feedback.
- Madhavan Swaminathan, PRC Director
5G Applications driven by Glass Interposer Solution
Millimeter-wave front end modules (FEM) require the integration of filters with high performance. The recent work at the PRC features panel-based, ultra-miniaturized filters with footprint smaller than half the free-space wavelength (0.5λ0✕0.5λ0) corresponding to the operating frequencies of 28 and 39 GHz bands for 5G and mm-wave small-cell applications. Two filter types: lowpass and bandpass, with three topologies in total, were modeled, designed and fabricated on precision thin-film buildup layers on an ultra-thin glass core. Semi-Additive Patterning (SAP) process was utilized to achieve fine line wiring. These filters can be embedded as integrated passive devices (IPDs) in electronic packages as a result of their small vertical height (188.5-µm). The simulated results of bandwidth, in-band insertion loss and out-of-band rejection of filters showed excellent correlation with measured results, indicating the ability to predict the process well. This work was supported by the industry consortium at PRC. PhD Student Muhammad Ali was recently recognized for this work with the 2019 Intel Best Student Paper Award at Electronics Components and Technology Conference (ECTC). Presented in IEEE 2018 ECTC, the title of Muhammad’s award-winning paper was "Miniaturized High-Performance Filters for 5G Small-Cell Applications.” His co-authors on the paper were his Ph.D. advisor, Prof. Rao Tummala along with Dr. Fuhan Liu, Atom Watanabe, Dr. Pulugurtha Markondeya Raj, Dr. Venkatesh Sundaram and Prof. Manos M. Tentzeris. Further details on the technology can be found here.
Hybrid-Digital-Mixed-Signal Computing Platform for Model-Based and Model-Free Swarm Robotics
An ultra-low power hybrid chip inspired by the brain could help give palm-sized robots the ability to collaborate and learn from their experiences. Combined with new generations of low-power motors and sensors, the new application-specific integrated circuit (ASIC) – which operates on milliwatts of power – could help intelligent swarm robots operate for hours instead of minutes. To conserve power, the chips use a hybrid digital-analog time-domain processor in which the pulse-width of signals encodes information. The neural network IC accommodates both model-based programming and collaborative reinforcement learning, providing the small robots larger capabilities for reconnaissance, search-and-rescue and other missions. Here, the goal is to bring intelligence to these very small robots so they can learn about their environment and move around autonomously, without infrastructure. To accomplish that, the team led by Prof. Arijit Raychowdhury hopes to bring low-power circuit concepts to these very small devices so they can make decisions on their own combined with advanced packaging technologies. The research was sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Semiconductor Research Corporation (SRC) through the Center for Brain-inspired Computing Enabling Autonomous Intelligence (CBRIC). The researchers demonstrated robotic cars driven by unique ASICs at the recent 2019 IEEE International Solid-State Circuits Conference (ISSCC).The paper details can be found here.
Packaging Architectures for Enabling Neuromorphic Computing
Alternate energy efficient analog computer architectures such as neuromorphic computing (NMC) are being investigated for IoTs (including smart phones) to reduce power consumption. A neuromorphic computer is a machine comprising many simple processors and memory structures (e.g. neurons and synapses) communicating using simple messages (e.g. spikes) mimicking the human brain. Enormous efforts have gone into inventing the ideal device that mimics neurons but less towards building a system (brain) out of these heterogeneous devices. SoC designs pose bottlenecks for neuromorphic computing and while 3D IC stacking is an option, through silicon vias (TSVs) can pose challenges. This presents an opportunity to develop newer packaging platforms to maximize performance and power efficiency, particularly for enabling edge-AI solutions. Though preliminary, researchers at PRC have proposed an architecture that uses a combination of 2.5D and 3D solutions, by integrating dielets (or chiplets) on an active interposer. This work was recently recognized with the 2019 IEEE EPS Packaging Vision award at the Electronics Components and Technology Conference (ECTC). This work was led by PhD students Shreya Dwarakanath, Chandra Nair and Siddharth Ravichandran
Application of Machine Learning for Integrated Package Design
Package integration creates uncertainties due to process variations. As systems become complex, the impact of such uncertainties can cause functional failures. Recent work at PRC introduces surrogate models to quantify such uncertainties. Based on the combination of two techniques, the Least Squares-Support Vector Machine (LS-SVM) and Gaussian Process (GP) regression, this work uses a surrogate model developed using a small set of model responses to construct a fast and accurate prediction of the efficiency of an Integrated Voltage Regulator (IVR). The nuance of this surrogate model, is that it provides an uncertainty associated with any prediction of the model output, i.e. creates conﬁdence intervals (CI), for any point in the input parameter space. The results show that the presented method provides accurate model prediction with its CI, while significantly reducing the CPU time as compared to Monte Carlo (MC) simulation. This work was supported by the European Union (EU) Project under the category “Internationalization of Research”, co-authored by Prof. Riccardo Trinchero (Politecnico di Torino, Italy), Prof. Flavio Canavero (Politecnico di Torino, Italy), Dr. Mourad Larbi and Prof. Madhavan Swaminathan and was recognized at the IEEE 2019 Workshop on Signal and Power Integrity (SPI) with the Best Paper Award. Further details on this work are available here.
||Prof. Tushar Krishna will have two of his recent research papers featured in the IEEE Micro
“Top Picks from Computer Architecture Conferences,” to be published in the May/June 2019
issue. One paper was selected as an IEEE Micro Top Pick, and another paper was selected as
an Honorable Mention. Krishna is an Assistant Professor in the School of Electrical and Computer
Engineering at Georgia Tech, with an Adjunct appointment in the School of Computer Science
Science. He received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts
Institute of Technology in 2014. Prior to that he received an M.S.E in Electrical Engineering from
Princeton University in 2009, and a B.Tech in Electrical Engineering from the Indian Institute of
Technology (IIT) Delhi in 2007. Before joining Georgia Tech in 2015, Dr. Krishna worked as a post-
doctoral researcher in the VSSAD Group at Intel, Massachusetts and at the Singapore-MIT Alliance
for Research and Technology (SMART) Center. Dr. Krishna’s research spans computer architecture,
interconnection networks, networks-on-chip (NoC), and AI accelerators - with a focus on optimizing
data movement in modern computing systems.He has over 40 publications in leading conferences
and journals, which have amassed over 4240 citations to date.
Min-Yu Huang, is a PhD student at Georgia Tech School of Electrical and Computer Engineering (ECE)
Hakki Mert Torun, is a PhD student at Georgia Tech in the School of Electrical and Computer
Center for Advanced Electronics through Machine Learning (CAEML) Fall Review | October 29-30th, 2019
3D Systems Packaging Packaging Research Center, IAB Meeting | November 7-8, 2019
IEEE EDAPS Symposium | December 16-18, 2019 in Kaohsiung, Taiwan http://edaps.org/